Complementary metal-oxide semiconductor (CMOS) integrated circuits are susceptible to CMOS latchup. CMOS latchup is an undesirable inherent phenomenon that creates a very low-resistance path between power supply rails in a CMOS integrated circuit, which causes large amounts of current to flow through the integrated circuit. The large amounts of current can prevent the CMOS integrated circuit from functioning properly and can even destroy the CMOS integrated circuit as a result of heat damage caused by high power dissipation. CMOS latchup is a well known and documented problem. See. e.g. Philip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design (Holt, Rinehart and Winston, Inc. 1987) and S. Wolf, Silicon Processing for the VLSI Era Vol. 2: Process Integration (Lattice Press 1990).
This high current latchup state results from complementary parasitic bipolar junction transistor structures (npn and pnp transistor structures) formed during the fabrication of the complementary MOS devices in CMOS integrated circuits. The complementary bipolar junction transistor structures can interact electrically due to being close to one another, which cause the structures to exhibit characteristics similar to a pnpn diode having three p-n junctions. The "pnpn diodes" operate as reverse-bias junctions when there is no trigger current established. Nevertheless, sufficient trigger currents are established during a number of frequently occurring abnormal circuit operation conditions to produce a sufficient positive loop gain to cause the parasitic bipolar junction transistor structures to enter a regenerative positive feedback latchup state. The positive feedback loop is formed because the collector of the npn transistor structure drives the base of the pnp transistor structure and the collector of the pnp transistor structure drives the base of the npn transistor structure. In the regenerative positive feedback latchup state, the loop gain (.beta..sub.npn .beta..sub.npn) exceeds unity. The regenerative positive feedback latchup state is manifested by a large amount of current drawn from the power supply through the "pnpn" structure. This large amount of current can significantly reduce or collapse the power supply voltage.
In order to recover from the high current latchup state, typically power must be removed from the integrated circuit die, thereby breaking the regenerative loop. Even if the integrated circuit die is restored to normal operation after excitation into the latchup state, the high latchup currents can cause significant reliability problems in the exposed integrated circuit die. Thus, CMOS latchup must be avoided in order to ensure the reliability of the integrated circuit die. Many approaches have been used to control, or to substantially eliminate CMOS latchup, such as with processing techniques and circuit layout procedures. Nevertheless, the ever decreasing CMOS integrated circuit dimensions has significantly heightened the severity of the latchup problem. Therefore, new CMOS latchup suppression techniques are needed to keep pace with the shrinking integrated circuit dimensions.
Memory integrated circuits, such as dynamic random access memories (DRAMs), are particularly prone to CMOS latchup when power is initially applied to the memory integrated circuit. This is especially true of large DRAMs, such as 256 Mbit and higher, which have significantly decreased dimensions between the parasitic bipolar junction transistor structures. In addition, these larger capacity DRAMs comprise memory arrays which have a very large capacitance relative to the substrate of the DRAM. This large capacitance can cause the substrate to couple up towards the regulated supply voltage (Vcc). The resulting increase in the substrate voltage (Vbb) can cause Vbb to increase to the point where certain of the "pnpn" parasitic diode junctions become forward biased and turn on the "pnpn" parasitic diodes to thereby trigger the regenerative positive feedback latchup state. The "pnpn" parasitic diode typically turns on in DRAMs with a base-emitter turn on voltage of approximately 0.7 volts. Therefore, there is a need for techniques to suppress CMOS latchup during power up of DRAMs and other such memory integrated circuits.